VHDL: Converting a Hexadecimal Value to a Standard Logic Vector

This example shows how to convert a hexadecimal value to a std_logic_vector.
It is shown in both VHDL ''87 (IEEE Std 1076-1987) and VHDL ''93 (IEEE Std 1076-1993).
For more information on using this example in your project, go to: http://www.fpga.com.cn


hex.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY hex IS
    PORT(
        D : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END hex;

ARCHITECTURE a OF hex IS
BEGIN
-- The following line will convert the hex value
-- to a STD_LOGIC_VECTOR in VHDL ''87.

    D(7 DOWNTO 0) <= to_stdlogicvector(x"FC");
   
-- The following line will work in VHDL ''93 (the standard allows
-- this conversion implicitly).
-- D <= x"FC";
END a;